In designing transmission equipment, the lines that carry data to and from certain pieces of equipment normally contain coding which generates specific line statistics. The coded data on these lines provides energy for the clock extraction circuits while keeping a zero DC offset in the line. A prior art solution has been to take the output from the encoding circuitry and "reverse engineer" the encoding in a line decode circuit and compare the output of the line decode circuit with a time delayed version of the input data. Whenever this decoded signal does not compare with the input, an error signal is generated. However, the line decode circuit requires a considerable amount of circuitry and it becomes very expensive to accomplish this function both in terms of cost of materials and the space required in the circuitry to provide this function. As will be realized by those skilled in the art, the decoding circuitry is typically more complicated than the original encoding circuitry.
A further possible approach to providing the error checking is to duplicate the encoding circuitry and then use a code synchronizer to synchronize the two encoding circuits. The code synchronizer is required because the encoding is dependent upon the polarity of the last pulse violating the bipolar rule utilized in the algorithm involved. In this approach to solving the problem, the code synchronizer is much more complicated than the remaining circuitry and is as undesirable an approach as the prior art solution mentioned above.
The circuitry used for detecting the specific condition of three consecutive logic zeros in the incoming signal is fairly simple. Also, the circuitry for changing the incoming NRZ (nonreturn to zero) data to bipolar data is very simple. The basis of the present invention, therefore, is to use a data comparison circuit for normally checking the logic values of the bipolar data except when the situation detected is the occurrence of three consecutive logic zeros. When this situation is detected, the data compare circuitry stops comparing data bits and instead compares whether or not both the encoding circuitry and the error checking or line detector circuit have both detected the condition simultaneously. If such simultaneous detection occurs, and the data previously output by the encoding circuit had been performing correctly up to that time, it is reasonable to assume that in the situation where the bipolar data is passed through all of the encoding circuit except for switched drivers at the very output, that the encoding circuity was operating correctly.
It is thus an object of the present invention to provide a more compact, low power circuit for checking the operation of an encoding circuit.